This invention relates to a synchronous binary counter in the form of a large scale integrated circuit for high speed digital signal processing.
The prior art synchronous binary counter has a construction as shown in FIG. 1. This construction has six bits constituted by respective J-K flip-flops FF1 to FF6. To the J and K terminals of each flip-flop are fed the AND of the positive outputs Q of all the lower bit flip-flops. To a clock input terminal of each flip-flop is fed clock pulse CK which is common to all the flip-flops. To the J and K terminals of the second highest bit, i.e., first stage, flip-flop is fed the positive output Q of the first stage. AND gates 31 to 34 are provided for the third to sixth stage flip-flops FF3 to FF6. AND gate 31 ANDs outputs of the bits lower than the third stage bit, i.e., outputs Q1 and Q2 of first and second stage flip-flops FF1 and FF2. It feeds an AND signal of the J and K input terminals of the third stage flip-flop FF3. Likewise, AND gate 32 ANDs the outputs of the bits lower than the fourth stage, i.e., outputs Q1 to Q3 of the first to third stage flip-flops FF1 to FF3, and it feeds the AND signal to the J and K input terminals of the fourth stage flip-flop FF4. Further, AND gate 33 ANDs the outputs of the lower bits than the fifth stage, i.e., outputs Q1 and Q4 of the first to fourth stage flip-flops FF1 to FF4, and it feeds the AND signal to the J and K input terminals of the fifth flip-flop FF5. Further, AND gate 34 ANDs the outputs of the lower bits than the last stage, i.e., outputs Q1 to Q5 of the first to fifth stage flip-flops FF1 to FF5, and it feeds the AND signal to the J and K input terminals of the last stage flip-flop FF6.
With the prior art synchronous binary counter as described above, the number of inputs to AND gates 31 to 34 is one more than the number of inputs for a stage that is higher by one bit, that is, the number of leads for the inputs is increased with increase of the order of the stage. Therefore, in the implementation of the integrated circuit, the input lead area is increased thus increasing the chip size and cost.
To cope with this problem, there has been proposed a construction as shown in FIG. 2. In this case, the inputs to the J and K input terminals of the third and higher stages are constituted by an AND of the input to the J and K input terminals and a positive output Q of one bit flip-flop from a lower stage, the AND signal being provided from each of AND gates 41 to 44, thus minimizing the input lead area for AND gates 41 to 44. With this construction, however, signal has to pass through all AND gates 41 to 44 until it reaches the J and K input terminals of the lowest order stage flip-flop FF1. This means that the operation speed of the counter is reduced.